Forget dual-core and quad-core processors: A semiconductor company promises to pack 100 cores into a processor that can be used in applications that require hefty computing punch, like video conferencing, wireless base stations and networking. By comparison, Intel’s latest chips are expected to have just eight cores.
“This is a general-purpose chip that can run off-the-shelf programs almost unmodified,” says Anant Agarwal, chief technical officer of Tilera, the company that is making the 100-core chip. “And we can do that while offering at least four times the compute performance of an Intel Nehalem-Ex, while burning a third of the power as a Nehalem.”
The 100-core processor, fabricated using 40-nanometer technology, is expected to be available early next year.
In a bid to beat Moore’s law (which states number of transistors on a chip doubles every two years), chip makers are trying to either increase clock speed or add more cores to a processor. But cranking up the clock speed has its limitations, says Will Strauss, principal analyst with research and consulting firm Forward Concepts.
“You can’t just keep increasing the clock speed so the only way to expand processor power is to increase the number of cores, which is what everyone is trying to do now,” he says. “It’s the direction of the future.”
In fact, Intel’s research labs are already working on a similar idea. Last year, Intel showed a prototype of a 80-core processor. The company has promised to bring that to consumers in about five years.
Tilera, a start-up that was spun out of the Massachusetts Institute of Technology, started in 2007. It says its product will be available in the next few months, which means the company, if successful, will have gone from zero to shipping a powerful chip in just about three years — a very fast time frame in the semiconductor world. That’s because it has created a chip architecture that removes the challenges present in Intel’s x86 design.
As the number of cores on a chip multiplies, a major challenge is how to connect the chip to memory without choking up the processor. That’s why Agarwal says Tilera has used a mesh network architecture. It eliminates the “on-chip bus interconnect,” a central intersection found in most multi-core CPUs through which information must flow through to get between the cores of a chip. That central interconnect presents bandwidth issues of its own, and also forces engineers to limit the number of cores on a chip to avoid information gridlock.
Instead, Tilera places a communication switch on each processor and arranges them in grid-like fashion on the chip. Because the overall bandwidth is greater than that of a central bus, and because the distance between individual cores is smaller, Tilera says it can cram in as many as 100 cores on a processor without running into bus-bandwidth congestion.
Each core has a full-featured, general-purpose processor that includes L1 and L2 caches, and a distributed L3 cache. The cores are overlaid with the mesh network, which provides extremely low-latency, high-bandwidth communications between the cores, memory and the processor’s input and output.
“If you need huge computing power, say for instance to encode and decode multiple video streams, our processor can do it at much more efficiency than Intel chip or a digital signal processor,” Agarwal says.
And unlike GPU-based computing systems, programmers can recompile and run applications and programs designed for Intel’s x86 architecture on Tilera’s processor.
“Tilera has put forth a novel approach to massively parallel programming,” Strauss says. “The 100-core processor is closer to a generic processor than anything else we have seen before.”
Don’t expect it to run Windows 7 on it though. For that, consumers will have to wait for Intel’s version in a few years.